1. Field of the Invention
The present invention relates to a method for thinning and planarizing a semiconductor layer by means of an etching treatment with locally varying material erosion.
2. Background Art
An example of a technologically relevant semiconductor layer is the functional layer of an SOI wafer (SOI=Semiconductor on Insulator or Silicon on Insulator). As their functional layer, SOI wafers comprise a semiconductor layer, for example a silicon layer, which lies on one surface of a base wafer (or handle wafer). The thickness of the semiconductor layer varies as a function of the components to be processed. Distinction is generally made between so-called thin films (less than 100 nm thick) and so-called thick films (from 100 nm to about 80 μm thick). Either the base wafer may consist entirely of an electrically insulating material (for example glass, quartz, sapphire) or it may for example consist of a semiconductor material, preferably silicon, and merely be separated from the semiconductor layer by an electrically insulating layer. The electrically insulating layer may, for example, consist of silicon oxide.
The semiconductor layer of an SOI wafer must have a very homogeneous thickness extending to the outermost edge region. Particularly in the case of semiconductor layers with a thickness of 100 nm or less, transistor properties, for example the threshold voltage, vary very greatly in the event of inhomogeneous layer thicknesses. The absolute thickness tolerance for SOI wafers with thin and thick semiconductor layers depends on the layer thickness.
In order to be able to integrate as large a number of circuits as possible, the requisite layer thickness homogeneity must furthermore be ensured as far as the vicinity of the edge of the front side. This in turn means a very small edge exclusion. The term “front side” of an SOI wafer refers to the side which carries the functional layer, on or in which electronic components are subsequently produced.
All known methods for producing SOI wafers attempt to adjust a sufficient homogeneity of the semiconductor layer directly, although for extreme requirements it may be necessary to carry out a post-treatment of the finished or semiprocessed SOI wafer in order to improve the thickness homogeneity further.
A plurality of methods for the post-treatment of an SOI wafer, with the aim of improving the layer thickness homogeneity, are known in the prior art. Many of these methods involve local etching methods while scanning over the SOI wafer, greater etching erosion being provided at positions with a higher layer thickness: according to US2004/0063329A1, in a dry etching method, the surface of the SOI wafer is scanned with a nozzle through which a gaseous etchant is delivered locally. EP488642A2 and EP511777A1 describe methods in which the semiconductor layer of the SOI wafer is exposed surface-wide to an etchant. This etchant must however be locally activated by a laser beam or a light beam from a light source, which is focused by an optical system, while scanning the surface (photochemical etching).
All methods in which the surface of the semiconductor layer needs to be scanned in order to achieve locally varying etching erosion, are very time-intensive and therefore cost-intensive. Furthermore, scanning requires an elaborate movement of the light source or the nozzle, on the one hand, or the SOI wafer on the other hand.
Furthermore, additional inhomogeneities of the layer thickness occur particularly in the edge region of the layer, i.e. in a region up to 5 mm away from the wafer edge, as well as in the regions where the overlap takes place during the scanning. For a layer thickness of 520 nm, a layer thickness homogeneity of 10 nm is achieved according to EP488642A2 without specifying an edge exclusion. According to EP511777A1, for a layer thickness of 108 nm, a layer thickness homogeneity of 8 nm is achieved without specifying an edge exclusion.
DE102004054566A1 describes a method for planarizing a semiconductor layer, in which—after position-dependent measurement of the thickness of the semiconductor layer—the SOI wafer is etched while exposing the entire surface of the wafer. The erosion rate of the etching treatment depends on the light intensity on the surface of the semiconductor wafer, and the light intensity is set position-dependently so that the differences in the previously measured position-dependent layer thickness are reduced by the position-dependent erosion rate. This method corrects local thickness differences of the semiconductor layer very effectively, although it requires additional outlay which increases the cost: a thickness measurement before the etching, the production of a mask for the exposure, and an exposure device.
JP09-008258A describes a method in which the silicon layer of an SOI wafer is etched with simultaneous exposure of the entire surface, and its thickness is homogenized. The process is self-regulating, because the etching rate depends on the number of holes (i.e. defect electrons, that is to say positive charge carriers) which are generated by the light, and therefore on the volume illuminated and consequently on the local silicon layer thickness over the insulating layer. Below a particular residual thickness of the silicon layer, the quantity of charge carriers generated by the light is no longer sufficient and the thinning stops. Since the absorption of light in the silicon layer also depends on the wavelength of the light, this approach furthermore makes it possible to adjust different residual thicknesses of the silicon layer. This method does not therefore require any external position-dependent regulating of the light intensity, or any thickness measurement before the etching, and no mask, although the etching device must still be constructed in an elaborate way such that that light can be directed appropriately.